• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    According to the present invention, data can be selectively inputted and outputted using a serial I / O switching latch and a parallel I / O switching latch so that the serial data input can be output as parallel data or a parallel data input can be output as serial data by a serial / parallel selection control signal. To a serial-to-parallel converter.
    公开号:KR19990038681A
    申请号:KR1019970058508
    申请日:1997-11-06
    公开日:1999-06-05
    发明作者:김시현
    申请人:구본준；엘지반도체 주식회사；
    IPC主号:
    专利说明:

    Serial to Serial Converter
    The present invention relates to a serial-to-parallel converter, and more particularly, to a serial-to-parallel converter that is adapted to output serial data input as parallel data or output parallel data input as serial data depending on the selection signal.
    In the conventional serial-to-parallel converter, as shown in FIG. 1, the serial transmission latches STL1-STL4 and the initialization signal SB, which are synchronized with the serial clock signal SCLK, are input and initialized, and the parallel clock is initialized. The signal PCLK is input and composed of parallel transmission latches PTL1-PTL4.
    The operation of the conventional serial / parallel converter will be described with reference to the accompanying drawings on the assumption that 4-bit input data ID is input in the conventional serial / parallel converter configured as described above.
    First, input data ID serially input as shown in FIG. 2C is input to the first serial transmission latch STL1 at each rising edge of the serial clock signal SCLK as shown in FIG. 2A. The data output from the serial transmission latch STL1 is input to the second serial transmission latch STL2 at the next rising edge of the serial clock signal SCLK. By repeating this method, the input data ID is input to each serial transmission latch STL1-STL4 without an indeterminate state. That is, when four bits of input data ID are inputted, four bits of serial input data ID are added to each serial transmission latch (STL1-STL4) after the rising edge of four serial clock signals SCLK passes. ) Is entered without an indeterminate state.
    Each parallel transmission latch (PTL1-PTL4) receives the serial input data (ID) inputted to each serial transmission latch (STL1-STL4), and then at the rising edge of the parallel clock signal (PCLK) as shown in FIG. 2B. Output data OD0-OD3 are output in parallel as shown in 2D to 2G.
    Here, each of the parallel transmission latch cells (Cell) is initially fixed to the high output value by the initialization signal (SB) as shown in Figure 2H, after the rising edge of the parallel clock signal (PCLK), Output normal serial input data (ID) as parallel output data (OD0-OD3).
    As described above, the serial-to-parallel converter of the prior art only outputs serial data inputs in parallel, and there is a problem in that parallel data inputs cannot be output in series.
    Accordingly, an object of the present invention is to enable selective output as parallel data when serial data is input and serial data when parallel data is input.
    In order to achieve the above object, the serial-to-parallel selection converter of the present invention includes a plurality of serial I / O conversion latches for serial data input or output, and a plurality of parallel I / O for parallel data input or output after being initialized by an initialization signal. A switching latch, a NAND gate to which a control signal and a serial-to-parallel selection control signal are input, an inverter for inverting the output of the NAND gate, an output of the NAND gate and an output of the inverter to control the parallel input / output switching latch. A plurality of transmission gates for transmitting the output or input of the D terminal and the Q terminal of the serial I / O switching latch, an inverter for inverting the serial / parallel selection control signal, and the serial / parallel selection control signal and its inverted signal. Input or output of the Q terminal of the serial I / O switching latch and the D terminal of the serial I / O switching latch of the next stage. A plurality of transmission gates to be transmitted, and a plurality of transmissions to control the outputs of the NAND gates and the outputs of the inverter to transmit inputs or outputs of the Q terminal of the serial I / O switching latch and the D terminal of the serial I / O switching latch of the next stage Characterized in that it comprises a transmission gate.
    1 is a block diagram of a series-parallel converter of the prior art.
    2 is an operation timing diagram in FIG. 1.
    3 is a block diagram of a serial-to-parallel converter of the present invention.
    4 is an operation timing diagram when outputting serial data input as parallel data in FIG. 3; FIG.
    5 is an operation timing diagram when outputting parallel data input as serial data in FIG. 3; FIG.
    6 is a circuit diagram of a parallel I / O switching latch cell of FIG. 3;
    7 is a circuit diagram of a series I / O switching latch cell of FIG. 3;
    ***** Description of symbols on the main parts of the drawings *****
    IN31-IN34, IN61-IN64, IN71-IN73: Inverter
    ND31, ND71: NAND Gate
    TG31-TG34, TGS31-TGS36, TG61-TG64, TG71TG74: Transmission Gate
    PM61-PM68, PM71-PM74: Pymotransistors
    NM61-NM68, NM71-NM74: NMOS transistors
    As shown in FIG. 3, the serial-to-parallel selection converter of the present invention includes an inverter IN31 for inverting the first external clock signal CK1, and a first external clock signal CK1 and its inverted signal CB1. Serial I / O switching latches SSL1-SSL4, in which the serial data is input or output by the serial-to-parallel selection control signal PSCtrl, and the inverter IN32 which inverts the second external clock signal CK2, and a reset. Parallel I / O initialized by the signal SB and synchronized with the second external clock signal CK2 and its inverted signal CB2, and parallel data is input or output by the serial / parallel selection control signal PSCtrl. A NAND gate ND31 to which the latches PSL1-PSL4, the control signal Ctrl and the serial / parallel selection control signal PSCtrl are input, and an inverter IN33 that inverts the output of the NAND gate ND31; Is controlled by the output of the NAND gate ND31 and its inverted signal. A transmission gate (TG31-TG34) connected between the D terminal of the parallel I / O switching latches (PSL1-PSL4) and the Q terminal of the serial I / O switching latches (SSL1-SSL4) and transmitting data, and the serial-to-parallel selection Inverter IN34 which inverts the control signal PSCtrl, and is controlled by the serial / parallel selection control signal PSCtrl and its inverted signal to switch the Q terminal of the serial I / O switching latch SSL and the serial I / O switching of the next stage. The serial input / output switching latch SSL is controlled by the transmission gates TGS31-TGS33 connected between the D terminals of the latch SSL to transmit data, and controlled by the output of the NAND gate ND31 and its inverted signal. It is composed of transmission gates (TGS34-TGS36) connected between the Q terminal of and the D terminal of the serial input / output conversion latch (SSL) of the next stage to transmit data.
    Here, the serial I / O switching latch SSL1-SSL4 and the parallel I / O switching latch PSL1-PSL4 are bidirectional latch cells in which an input / output function is switched by a latch control signal PSCtrl.
    As shown in FIG. 6, the series I / O switching latch SSL1-SSL4 includes a first PMOS transistor latch unit PL1 and a first NMOS transistor latch connected in series between a supply voltage VDD and a ground voltage VSS. An inverter IN61 having an input connected to the first PMOS transistor latch unit PL1 and the first NMOS transistor latch unit NL1 in common and outputting a first switching signal CO1; A second PMOS transistor latch unit PL2 and a second NMOS transistor latch unit NL2 connected in series between a supply voltage VDD and a ground voltage VSS, and an input of the second PMOS transistor latch unit An inverter IN62 which is commonly connected to PL2) and the second en-transistor latch unit NL2 and outputs a second switching signal CO2, and an inverter IN63 that inverts the serial / parallel selection control signal PSCtrl; The D and Q terminals are controlled by the serial and parallel selection control signal PSCtrl and its inverted signal. The transmission gates TG61-TG64 for transmitting data and an input thereof are commonly connected to the first PMOS transistor latch unit PL1 and the first NMOS transistor latch unit NL1, and an output thereof is transmitted. An inverter IN64 connected to the gate TG64 is configured.
    Here, the first PMOS transistor latch unit PL1 is connected to a gate connected in series between a supply voltage VDD and a first NMOS transistor latch NL1, respectively, to the first switching signal CO1 and the first external clock. The PMOS transistors PM61 and PM62 to which the signal CK1 is input, respectively, and the inverted signal CB1 of the second switching signal CO2 and the first external clock signal CK1 to the gate, respectively. It includes morph transistors (PM63, PM64), the source of the PMOS transistors (PM61, PM63) are connected in common, the drain of the PMOS transistors (PM62, PM64) is configured in common.
    The second PMOS transistor latch unit PL2 is a PMOS transistor having a terminal D connected to a gate connected in series between a supply voltage VDD and a second NMOS transistor latch NL2 through a transfer gate TG62. (PM65), a PMOS transistor (PM66) to which the first external clock signal (CK1) is input to the gate; and a PMOS transistor (PM63) to which the second switching signal (CO2) is input to the gate; And the PMOS transistors PM67 and PM68 to which the inverted signal CB1 of the second switching signal CO2 and the first external clock signal CK1 are input, respectively, and includes the PMOS transistors PM65 and PM67. The source is connected in common and the drains of the PMOS transistors PM66 and PM68 are connected in common.
    The first NMOS transistor latch unit NL1 is an inverted signal CB1 of the first external clock signal CK1 at a gate connected in series between the first PMOS transistor latch unit PL1 and the ground voltage VSS. ) And the NMOS transistors NM61 to which the first switching signal CO1 is input, and the NMOS63 transistors NM63 to which the first external clock signal CK1 and the second switching signal CO2 are respectively input to the gate. And NM64, wherein the drains of the NMOS transistors NM61 and NM63 are connected in common, and the sources of the NMOS transistors NM62 and NM64 are connected in common.
    The second NMOS transistor latch unit NL2 is an inverted signal CB1 of the first external clock signal CK1 at a gate connected in series between the second PMOS transistor latch unit PL2 and the ground voltage VSS. ) Is input to the NMOS transistor NM65, the gate is connected to the D terminal via the transfer gate TG62, and the NMOS transistor NM66, and the gate is connected to the first external clock signal CK1 and the second switching signal. Each of the NMOS transistors NM67 and NM68 to which CO2 is input, the drains of the NMOS transistors NM65 and NM67 are connected in common, and the sources of the NMOS transistors NM66 and NM68 are respectively connected. Common connection is made.
    As shown in FIG. 7, the parallel I / O switching latches PSL1-PSL4 have a third PMOS transistor latch unit PL3 and a third NMOS transistor latch connected in series between a supply voltage VDD and a ground voltage VSS. And the inverter NL3, the inverter IN71 in which the serial / parallel selection control signal PSCtrl is inverted, and the serial / parallel selection control signal PSCtrl and its inverted signal to control data between the D terminal and the Q terminal. It is connected to the transmitting gates TG71-TG74, the third PMOS transistor latch unit PL3, and the third NMOS transistor latch unit PL3 in common and is input to the first input terminal, and a reset signal. A NAND gate ND71 to which SB is input to the second input terminal, and inverters IN72 and IN73 whose outputs of the NAND gate ND71 are sequentially inverted.
    Here, in the third PMOS transistor latch unit PL3, a gate connected in series between the supply voltage VDD and the third NMOS transistor latch unit NL3 is connected to the P terminal through the transfer gate TG72. A transistor PM71 and a PMOS transistor PM72 to which the inverted signal CB2 of the second external clock signal CK2 is input to the gate, an output of the NAND gate ND71 to the gate, and a second external clock signal to the gate. PMO transistors PM73 and PM74 to which CK2 is input, respectively, sources of the PMO transistors PM71 and PM73 are connected in common, and drains of the PMO transistors PM72 and PM74 are connected to each other. Common connection is made.
    The third NMOS transistor latch unit NL3 includes an NMOS transistor in which a second external clock signal CK2 is input to a gate connected in series between the third PMOS transistor latch unit PL3 and the ground voltage VSS. NM71, and the NMOS72 transistor NM72 whose gate is connected to the D terminal through the transmission gate TG72, the inverted signal CB2 of the second external clock signal CK2 at the gate, and the NAND gate ND71. Including the nMOS transistors NM73 and NM74 to which the output signal is inputted, drains of the nMOS transistors NM71 and NM73 are commonly connected, and the sources of the nMOS transistors NM72 and NM74 are common. It is connected and configured.
    The operation of the serial-to-parallel selection converter of the present invention configured as described above will be described in detail with reference to the accompanying drawings.
    First, in case of serial input / output switching latch (SSL1-SSL4) and parallel input / output switching latch (PSL1-PSL4), when the serial / parallel selection control signal PSCtrl is low level, that is, "0", the D terminal is the input terminal and the Q terminal. When the serial / parallel selection control signal PSCtrl is high level, that is, "1", the D terminal is an output terminal and the Q terminal is an input terminal.
    Therefore, as shown in FIG. 4, when the serial and parallel selection control signal PSCtrl and the control signal Ctrl are at the low level, the serial I / O switching latch SSL1-SSL4 and the parallel I / O switching latch PSL1-PSL4. ), D terminal is the input terminal, Q terminal is the output terminal.
    At this time, the first serial I / O switching latch SSL1 receives data at the rising edge of the first external clock signal CK1 as shown in FIG. 4A and transmits the data to the second serial I / O switching latch SSL2. Will print If the above operation continues and the input of the serial data SIO as shown in Fig. 4C is completely set to each serial I / O switching latch SSL1-SSL4 by the first external clock signal CK1, The parallel I / O switching latches PSL1-PSL4, which are all set to "1" by the initialization signal SB as shown in 4H, are applied at the rising edge of the second external clock signal CK2 as shown in FIG. 4B. The data set in the serial I / O switching latch SSL1-SSL4 is output as parallel data PIO0-PIO3 as shown in FIGS. 4D to 4G.
    On the contrary, as shown in FIG. 5, when the serial / parallel selection control signal PSCtrl is high level and the control signal Ctrl is low level, the input terminal of the serial input / output switching latch SSL, that is, the Q terminal, is The output terminal of the serial input / output switching latch (SSL) of the next stage, that is, the output of the D terminal is not affected.
    At this time, when the parallel data PIO0-PIO3 as shown in FIGS. 5D to 5G are input, the parallel I / O switching latches PSL1 to PSL4 at the rising edge of the second external clock signal CK2 as shown in FIG. 5B. ) Respectively transmits data to the corresponding serial I / O switching latches SSL1-SSL4, and then, when the control signal Ctrl becomes high level, the input terminal of the serial I / O switching latch SSL, that is, the Q terminal and The output terminal of the serial input / output switching latch (SSL) of the next stage, that is, the D terminal, is connected. Therefore, the data input to the serial I / O switching latches SSL1-SSL4 is sequentially output as serial data SIO for each rising edge of the first external clock signal CK1.
    Therefore, the serial-to-parallel selection converter of the present invention described in detail above can output the data inputted in series by the serial-parallel selection control signal in parallel, and also can output the data inputted in parallel in series. There is.
    权利要求:
    Claims (4)
    [1" claim-type="Currently amended] A plurality of serial I / O switching latches for inputting or outputting serial data, a plurality of parallel I / O selection switching latches for inputting or outputting parallel data after being initialized by an initialization signal, and a control signal and a serial / parallel selection control signal An output of the NAND gate, an inverter for inverting the output of the NAND gate, an output of the NAND gate and an output of the inverter, and an output of the D terminal of the parallel I / O selection switching latch and the Q terminal of the series I / O switching latch, or A plurality of transmission gates for transmitting an input, an inverter for inverting the serial / parallel selection control signal, and a series of Q terminals of the serial I / O switching latch and the next stage, controlled by the serial / parallel selection control signal and its inverted signal. A plurality of transfer gates which transfer an input or an output of the D terminal of the input / output switching latch, and outputs of the NAND gate; And a plurality of transmission gates controlled by an output of the inverter to transmit inputs or outputs of the Q terminal of the serial I / O switching latch and the D terminal of the serial I / O switching latch of the next stage. converter.
    [2" claim-type="Currently amended] The serial-to-parallel selection converter according to claim 1, wherein the serial I / O switching latch and the parallel I / O switching latch are bidirectional latch cells in which a function of input / output is switched by a latch control signal.
    [3" claim-type="Currently amended] 2. The serial input / output switching latch and the parallel input / output switching latch according to claim 1, wherein the D terminal is an input terminal and the Q terminal is an output terminal when the serial / output switching latch is at a low level, and the D / Q switching terminal is at a high level. A serial / parallel selection converter, wherein the terminal is an output terminal and the Q terminal is an input terminal.
    [4" claim-type="Currently amended] 2. The input terminal of the serial I / O switching latch, i.e., the output terminal of the serial input / output switching latch of the next stage, i.e., Q, when the serial / parallel selection control signal is high level and the control signal is low level. Serial-to-parallel converter characterized in that the output of the terminal is not affected.
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    同族专利:
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    KR100253343B1|2000-04-15|
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-11-06|Application filed by 구본준, 엘지반도체 주식회사
    1997-11-06|Priority to KR1019970058508A
    1999-06-05|Publication of KR19990038681A
    2000-04-15|Application granted
    2000-04-15|Publication of KR100253343B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019970058508A|KR100253343B1|1997-11-06|1997-11-06|Direct- parallel select converter|
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